Texas Instruments Japan Ltd. April 1988- September 1993: Worked as Design Engineer at Texas Instruments Japan Ltd., Tokyo Design Centre from April 1988 to October 1993. Worked in the research and development of Bi-CMOS process for mixed analog digital Very Large Scale Integrated (VLSI) circuit design. My primary responsibility included research on process flow and doping profile design, design and layout of Process Control Bar (PCB), process characterization, extraction and fitting of SPICE MOS model parameters. We developed a 1.2 micron double metal Bi-CMOS process which was the leading Bi-CMOS process at Texas Instruments Japan Ltd. at that time. The process had 1.2 micron CMOS with 6.0 GHz vertical NPN transistor, 1.5 GHZ vertical PNP transistor and nitride capacitor. The process was used for the design of many mixed Analog/Digital VLSI chips at Texas Instruments, Japan.
Hiroshima University, Japan. July 2001 – June 2003: Visiting Research fellow, Research Center for Nanodevices and Systems, Hiroshima University, Japan. Worked on the development of a novel interconnect technology for intra-chip and inter-chip wireless clock and data transmission using integrated antenna . We have demonstrated for the first time very small size integrated antenna (0.02 mm2) with very high transmission gain (-15 dB at 25 GHz at a distance of 3mm) achieved by proton implantation on a Si substrate. We have also demonstrated, excitation technique which enable integrated antenna on a Si chip to propagate signals without suffering reduction of transmission gain due to the neighboring metal layers in a multi-level metal process.
Bangladesh university of engineering and technology (BUET) :
Professor : Feb2006 - to DATE
Associate Professor : May 2000 - Feb 2006
Assistant Professor : Oct 1996 - May 2000