Course Information                                                

              EEE457 VLSI II

                     Lecture Plan

                     Process Enhancement (Removed)

                     Nanometer Process Flow (Removed)

                     Adders and Multipliers (Removed)

                     High Speed (Removed)

                     Circuit Families (Removed)

                     Data Path (removed)

                     Sequential Circuit Design (Removed)

                     Synchronous Sequential Circuit Design (Removed)

                     Methodology (Removed)

                     Memory  Array (Removed)

                     Low Power Circuit Design (Removed)

                     VLSI Testing (Removed)

                     System Verilog Introduction (Removed)

                    EEE458 VLSI II Laboratory

                      Process Design Kit for EEE 458

                      Lab 2 : Layout Design of a 2 input NAND gate (Removed)

                     Lab 3 : 2 Input NAND gate DRC,  LVS  comparison, and Parasitic Extraction (Removed)

                     Lab Report Submission Template (Removed) 

                     Lab 4 Incisive Unified Simulator (Removed)    

                     Lab6 Place and Route (removed)   

                     Lab 7 Schematic Driven Layout (removed)         

                          Project of VLSI II Sessional (Removed)

                 EEE453 VLSI I

                     Inverter 

                     Fabrication

                     gpdk090_DRM.pdf

                     Logic Structures 

                         ALU 

                          Memory

                     Synchronous System State Machine Design

                     Testing VLSI 

            EEE 454 VLSI I Laboratory

                    Lab Report Submission Template

                    Lab4 Layout (removed)

                    Lab5 Ring Oscillator Buffer (removed)  

                    Project of VLSI I Sessional (Removed)